The present invention relates to a flat-type housing semiconductor device having a plurality of semiconductor chips which are connected in parallel in a single package and to a power converter employing the same.
The power-electronics technology which controls main circuit current by means of the semiconductor electronics technology has been used in various applicable fields and further its application range is expanding. Recently, in particular, the world has been paying great attention to insulated-gate bipolar transistors (IGBT) and metal-oxide-silicon field-effect transistors (MOSFET) which are MOS control devices using signals applied to MOS gates to control main currents. The IGBTS, for example, have been widely used as power-switching devices for motor pulse-width-modulation (PWM) inverters.
Said MOS control device has main electrodes (emitter electrodes) and control electrodes (gate electrodes) disposed on the primary surface of the semiconductor chip and main electrodes (collector electrodes) on the secondary surface of the chip.
Accordingly, when a semiconductor package is made, the main electrodes and control electrodes on the primary surface must be lead out separately and individually through the external leads. For this purpose, the conventional module type packages such as the IGBT employs forming main electrodes for the secondary surface directly on the metallic base which also works as a radiator, wire-bonding the main electrodes (emitter electrodes) and the control electrodes (gate electrodes) to the related external leads with electrically-conductive wires such as aluminum wires, and thus leading them out of the package. Recently, larger-capacity semiconductor chips have been required eagerly. As one of such semiconductor chips, there has been a module type package having a plurality of IGBT chips (few chips to ten chips) whose electrodes are interconnected in parallel by wire-bonding. Such a package radiates heats generated in the package only from one side of the package, namely from the side of collectors which are directly formed on the metallic base. Therefore, such a package has a great thermal resistance and the capacitance of the semiconductor chip is limited to by the number of chips to be mounted and the amperage that is used. As the amperage increases, more wires are required to connect emitter electrodes. Consequently, the inductance of the internal wiring increases and may cause a great surge at the time of switching. As the number of elements in a package increases further, connection of bonding-wires becomes much complicated, which may cause a wire disconnection or short-circuit in the package. Additionally, when a big current is fed to the package, fine bonding wires may be easily blown out by a resulting heat.
To solve said problems, a pressure-contact type package has been proposed. Said package contains IGBT chips in a flat-type package. Their emitter and collector electrodes formed on the main surface are respectively in contact with upper and lower electrodes formed in the package.
For example, Fuji Report Vol.69, No.5 (1996) discloses a flat-type IGBT package of a breakdown voltage of 2.5 KV and an ampacity of 1 KA which includes 12 semiconductor chips (9 IGBT chips and 3 diodes). In Japanese Non-examined Patent Publication No.7-94673, there is disclosed such a flat-type IGBT package that includes 5 IGBT chips and 1 diode.
A representative structural example of said package is illustrated in FIG. 17. As shown in FIG. 17, the secondary surface (working as a collector) of respective chips 1 and 2 is soldered 61 to a single electrode substrate (Mo) 61 formed on a common electrode plate 8 (Cu) of the package. The primary surface (working as an emitter) of each chip is connected to a common electrode plate 7 (Cu) of the package via respective contact terminal element 63 or 64 (Mo) that is separated for each chip. Each semiconductor chip is positioned and secured upright on a predetermined location by positioning guide 66 which is inserted into a slit provided around the chip-mount area on said electrode substrate 61 (Mo). In other words, this positioning guide 66 is used as an outer frame guide to retain the semiconductor chips 1 and 2 and contact terminal elements 63 and 64. The control electrode (gate electrode) of each semiconductor chip is connected to a wiring net on the wiring base 67 provided around the collector electrode substrate 61 by wire-bonding. Further, the contact terminal element has a concave notch to avoid touching the wires.
Similarly, Japanese Non-examined Patent Publication No.8-88240 discloses an embodiment of a flat-type IGBT package containing 21 semiconductor chips (9 IGBTs and 12 diodes). FIG. 18 shows a representative structural example of said package. As shown in FIG. 18, the secondary surface (working as a collector) of respective chips 1 and 2 is formed on a single electrode substrate (Mo) 61 of a common electrode plate 8 (Cu) of the package. The primary surface (working as an emitter) of each chip is connected to a common electrode plate 7 (Cu) of the package via respective pressure-contact plate 63 or 64 (Mo) that is separated for each chip. Each semiconductor chip is positioned and secured by a chip frame 70 formed on each semiconductor chip.
In other words, a chip frame 70 is formed on the outer periphery of each semiconductor chip. The chip frames are arranged in a close-contact manner on an identical surface. The outermost close-contact chip frames are enclosed by an external frame 71. Thus the respective chips are positioned finally. Each chip frame enables securing the chip and the pressure-contact plate 63 or 64 and the external frame 71 positions the gate electrode 4 exactly. The front end of a probe 72 touches the gate electrode 4 of each semiconductor chip. The probe is lead out to the outside of the package by a gate lead wire 74 for respective chip connected to the probe by a socket 73. A groove 75 is formed on the inner surface (pressure-contact surface) of the emitter electrode plate 7 where the chips are in contact with each other (around a portion opposite the semiconductor chip). A plurality of said gate leads 74 are disposed in this groove 75.
Said flat-type housing structures have the following merits in comparison to the conventional module-type packages:
1) Non-wire-connection of main electrodes increases the reliability of connection.
2) The inductances and resistances of connection wires decrease.
3) The semiconductor chip can be cooled at both sides of the chip. This increases the efficiency of cooling.
However, when a semiconductor package requires a great number of semiconductor chips in parallel connection, for example, tens to hundred semiconductor elements for a larger capacity, the packaging methods in the above disclosed embodiments are not enough. In such a case, exact chip positioning and gate wiring may be hard to be accomplished. Furthermore, a great number of gate wires may cause generation of noises and the like which cannot be ignored in the gate circuits due to the increase of wiring inductance. Furthermore, if the breakdown voltage of the chips is increased to satisfy the high breakdown voltage requirement, the chips generate greater heat. This heat causes members of the package to expand and consequently causes positional differences of the members. Therefore, the conventional packaging method is not fit for production of large packages of a high breakdown voltage and a great ampacity.
The present invention has been made considering said problems. It is therefore, an object of the present invention to provide a method of positioning a great number of semiconductor chips in a large flat-type housing semiconductor package at high precision, at low cost, and in a simple way. Another object of the present invention is to make gate signal wiring of a package containing a number of chips simpler and highly reliable. A further object of the present invention is to present power converting equipment which is fit for a large-capacity system by using the above semiconductor device.
Said first object can be accomplished by giving a function of positioning respective semiconductor chips in the flat-type package to control electrode wires led out from the control electrode of each semiconductor chip and to the insulating member which insulates the wires from the main electrode wires. Preferably the flat-type package should be so constructed that the intermediate electrode formed on the primary main electrode of a semiconductor chip may have a through-hole or a notch and that a control electrode wire coming from the control electrode on the semiconductor chip may connect said through-hole (or notch) made on the intermediate electrode and a hole (or groove) formed in the common electrode plate opposite to the primary main electrode. This structure thus works to lead out control electrode wires from the control electrodes of semiconductor chips and to position said intermediate electrodes relative to the common electrode plate.
Another object of the present invention to make gate signal wiring of a semiconductor package containing a number of chips simpler and highly reliable can be accomplished by housing the net of control electrode wires in the common electrode of the package and connecting the wires led out from the control electrode of each semiconductor chip to the net. It is more preferable that the control electrode wire net formed inside the common electrode of said package is formed in a unit, that the net is formed in a groove provided on the surface of the common electrode, that said groove runs through the related portion of the control electrode of the opposing semiconductor chip, and that the surface which is electrically connected to said led-out electrode of said control electrode wire net faces to the semiconductor chip.
Furthermore, the use of a flat-type semiconductor device of a high breakdown voltage and a great ampacity which contains a number of MOS control devices (IGBT chips) in accordance with the present invention can greatly reduce the volume and production cost of packages in comparison to conventional power converting devices using GTO and the like which have been used in fields requiring high breakdown voltages and great ampacities.